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CY62158EV30 MoBL(R)
8-Mbit (1024K x 8) Static RAM
Features
* Very high speed: 45 ns -- Wide voltage range: 2.20V-3.60V * Pin compatible with CY62158DV30 * Ultra low standby power -- Typical standby current: 2 A -- Maximum standby current: 8 A * Ultra low active power * * * * -- Typical active current: 1.8 mA @ f = 1 MHz Easy memory expansion with CE1, CE2, and OE features Automatic power down when deselected CMOS for optimum speed/power Offered in Pb-free 48-ball VFBGA, 44-pin TSOP II and 48-pin TSOP I packages[1]
Functional Description [2]
The CY62158EV30 is a high performance CMOS static RAM organized as 1024K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Placing the device into standby mode reduces power consumption significantly when deselected (CE1 HIGH or CE2 LOW). The eight input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and OE LOW while forcing the WE HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins. See the "Truth Table" on page 8 for a complete description of read and write modes.
Logic Block Diagram
CE1 CE2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 WE OE
DATA IN DRIVERS ROW DECODER
IO0 IO1 SENSE AMPS IO2 IO3 IO4 IO5 IO6
1024K x 8 ARRAY
COLUMN DECODER
POWER DOWN
IO7
A15 A16 A17
A13 A14
Notes 1. For 48 pin TSOP I pin configuration and ordering information, please refer to CY62157EV30 Data sheet. 2. For best practice recommendations, refer to the Cypress application note "System Design Guidelines" at http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05578 Rev. *D
*
198 Champion Court
A18
A19
*
San Jose, CA 95134-1709
* 408-943-2600 Revised April 19, 2007
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CY62158EV30 MoBL(R)
Pin Configurations [3]
48-Ball VFBGA
Top View 1 NC NC IO 0 VSS VCC IO 3 NC A18 2 OE NC NC IO1 IO 2 NC NC A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 NC IO5 IO 6 NC WE A11 6 CE2 NC IO 4 VCC VSS IO 7 NC A19 A B C D E F G H A4 A3 A2 A1 A0 CE1 NC NC IO 0 IO 1 VCC VSS IO 2 IO 3 NC NC WE A19 A18 A17 A16 A15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
44-Pin TSOPII
Top View A5 A6 A7 OE CE2 A8 NC NC IO 7 IO 6 VSS VCC IO 5 IO 4 NC NC A9 A10 A11 A12 A13 A14
Product Portfolio
Power Dissipation Product Min CY62158EV30LL 2.2 VCC Range (V) Typ[4] 3.0 Max 3.6 45 Speed (ns) Operating ICC (mA) f = 1 MHz Typ[4] 1.8 Max 3 f = fmax Typ[4] 18 Max 25 Standby, ISB2 (A) Typ[4] 2 Max 8
Notes 3. NC pins are not connected on the die. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C.
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Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential -0.3V to VCC(max) + 0.3V DC Voltage Applied to Outputs in High-Z State[5, 6] ......................... -0.3V to VCC(max) + 0.3V DC Input Voltage[5, 6] ..................... -0.3V to VCC(max) + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Latch up Current...................................................... >200 mA
Operating Range
Product Range Ambient Temperature (TA) VCC[7]
CY62158EV30LL Industrial
-40C to +85C 2.2V - 3.6V
Electrical Characteristics (Over the Operating Range)
Parameter VOH VOL VIH VIIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Test Conditions IOH = -0.1 mA IOH = -1.0 mA, VCC > 2.70V IOL = 0.1 mA IOL = 2.1 mA, VCC > 2.70V VCC = 2.2V to 2.7V VCC = 2.7V to 3.6V VCC = 2.2V to 2.7V VCC = 2.7V to 3.6V GND < VI < VCC GND < VO < VCC, Output Disabled f = 1 MHz ISB1 Automatic CE Power down Current -- CMOS Inputs Automatic CE Power down Current -- CMOS Inputs VCC = VCCmax IOUT = 0 mA CMOS levels 1.8 2.2 -0.3 -0.3 -1 -1 18 1.8 2 45 ns Min 2.0 2.4 0.4 0.4 VCC + 0.3V VCC + 0.3V 0.6 0.8 +1 +1 25 3 8 Typ[4] Max Unit V V V V V V V V A A mA mA A
VCC Operating Supply Current f = fmax = 1/tRC
CE1 > VCC - 0.2V, CE2 < 0.2V VIN > VCC - 0.2V, VIN < 0.2V) f = fmax (Address and Data Only), f = 0 (OE and WE), VCC = 3.60V CE1 > VCC - 0.2V or CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V
ISB2[8]
2
8
A
Capacitance[9]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Notes 5. VIL(min) = -2.0V for pulse durations less than 20 ns. 6. VIH(max)= VCC + 0.75V for pulse duration less than 20 ns. 7. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 8. Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 9. Tested initially and after any design or process changes that may affect these parameters.
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Thermal Resistance[9]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board BGA 72 8.86 TSOP II 76.88 13.52 Unit C/W C/W
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC GND 10% ALL INPUT PULSES 90% 90% 10%
Rise Time: 1 V/ns Equivalent to: THEVENIN EQUIVALENT
RTH OUTPUT VTH
Fall time: 1 V/ns
Parameters R1 R2 RTH VTH
2.5V 16667 15385 8000 1.20
3.0V 1103 1554 645 1.75
Unit V
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR[8] tCDR[9] tR[10] Description VCC for Data Retention Data Retention Current VCC = 1.5V, CE1 > VCC - 0.2V or CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Conditions Min 1.5 2 5 Typ[4] Max Unit V A
Chip Deselect to Data Retention Time Operation Recovery Time
ns ns
Data Retention Waveform
VCC
CE1
VCC, min tCDR
DATA RETENTION MODE VDR > 1.5V
VCC, min tR
or
CE2
Note 10. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
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Switching Characteristics (Over the Operating Range) [11]
Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Cycle[14] Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High Z[12, 13] 10 WE HIGH to Low Z[12] 45 35 35 0 0 35 25 0 18 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[12] OE HIGH to High Z[12, 13] CE1 LOW and CE2 HIGH to Low CE1 HIGH or CE2 LOW to High Z[12] 10 18 0 45 Z[12, 13] 5 18 10 45 22 45 45 ns ns ns ns ns ns ns ns ns ns ns Description 45 ns Min Max Unit
CE1 LOW and CE2 HIGH to Power Up CE1 HIGH or CE2 LOW to Power Down
Notes 11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in "AC Test Loads and Waveforms" on page 4. 12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 13. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 14. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
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CY62158EV30 MoBL(R)
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[15, 16]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled)[16, 17]
ADDRESS tRC CE1 CE2 tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE
ICC ISB
Notes 15. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 16. WE is HIGH for read cycle. 17. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
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CY62158EV30 MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[14, 18, 19]
tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tPWE tHA
OE tSD DATA IO NOTE 20 tHZOE VALID DATA tHD
Write Cycle No. 2 (CE1 or CE2 Controlled)[14, 18, 19]
tWC ADDRESS tSCE CE1 tSA CE2 tAW tPWE WE tHA
OE tSD DATA IO VALID DATA tHD
Notes 18. Data IO is high impedance if OE = VIH. 19. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 20. During this period, the IOs are in output state. Do not apply input signals.
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Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[19]
tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tSD DATA IO NOTE 20 tHZWE VALID DATA tLZWE tHD tPWE tHA
Truth Table
CE1 H X L L L CE2 X L H H H WE X X H H L OE X X L H X Inputs/Outputs High Z High Z Data Out High Z Data in Mode Deselect/Power Down Deselect/Power Down Read Output Disabled Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 45 Ordering Code CY62158EV30LL-45BVXI CY62158EV30LL-45ZSXI Package Diagram Package Type Operating Range Industrial
51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free) 51-85087 44-pin TSOP II (Pb-free)
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CY62158EV30 MoBL(R)
Package Diagrams
Figure 1. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
TOP VIEW BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C 1.00 MAX
SEATING PLANE 0.26 MAX. C
51-85150-*D
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CY62158EV30 MoBL(R)
Package Diagrams (continued)
Figure 2. 44-Pin TSOP II, 51-85087
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Document History Page
Document Title: CY62158EV30 MoBL(R), 8-Mbit (1024K x 8) Static RAM Document Number: 38-05578 REV. ** *A *B ECN NO. 270329 291271 444306 Issue Date See ECN See ECN See ECN Orig. of Change PCI SYT NXR New Data Sheet Converted from Advance Information to Preliminary Changed ICCDR from 4 to 4.5 A Converted from Preliminary to Final. Removed 35 ns speed bin Removed "L" bin. Removed 44 pin TSOP II package Included 48 pin TSOP I package Changed the ICC Typ value from 16 mA to 18 mA and ICC max value from 28 mA to 25 mA for test condition f = fax = 1/tRC. Changed the ICC max value from 2.3 mA to 3 mA for test condition f = 1MHz. Changed the ISB1 and ISB2 max value from 4.5 A to 8 A and Typ value from 0.9 A to 2 A respectively. Updated Thermal Resistance table Changed Test Load Capacitance from 50 pF to 30 pF. Added Typ value for ICCDR . Changed the ICCDR max value from 4.5 A to 5 A Corrected tR in Data Retention Characteristics from 100 s to tRC ns Changed tLZOE from 3 to 5 Changed tLZCE from 6 to 10 Changed tHZCE from 22 to 18 Changed tPWE from 30 to 35 Changed tSD from 22 to 25 Changed tLZWE from 6 to 10 Updated the ordering Information and replaced the Package Name column with Package Diagram. Included 44 pin TSOP II package in Product Offering. Removed TSOP I package; Added reference to CY62157EV30 TSOP I Updated the ordering Information table Added footnote #8 related to ISB2 and ICCDR Description of Change
*C
467052
See ECN
NXR
*D
1015643
See ECN
VKN
Document #: 38-05578 Rev. *D
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